A so-called video format signal, like that of a composite video signal, consists of successive field signals each having a picture information signal portion, horizontal and vertical synchronizing signal portions, and horizontal and vertical blanking signal portions. In general, a pair of field signals form one frame signal.
If a writing operation of an input video format signal into a picture memory is initiated at a first start time, and a reading-out operation of the written video format signal from the picture memory is initiated at a second start time (which is different from that of the first start time of the writing operation). it is possible to obtain a video format signal outputted from the picture memory which is different in phase from the video format signal inputted to the picture memory. In video format processing systems, the picture data which is written-into and read-out of the picture memory is obtained by sampling an input video format signal according to a predetermined period. In such processing systems, it is necessary (in order to increase the operating speed of the system) to provide a serial-to-parallel (hereinafter referred to as "S-P") converter, and a parallel-to-serial (hereinafter referred to as "P-S") converter, at the writing (input) and reading (output) sides of the picture memory, respectively. In such processing systems, the S-P conversion period is selected to be M times as long as the sampling period, wherein M-samples of the video format signal correspond to one address of the picture memory. Further, it is desirable to select the time-length of the picture data stored in one address of the picture memory to be equal to or an integer times as long as a subcarrier period, thereby allowing sufficient time to take into account those situations where special effects (e.g. reduction, enlargement, displacement, dropout-correction, etc.) of the picture data is performed. More particularly, in such situations, picture data is read-out of the memory according to a sequence of addresses which is different from that in a normal reading operation. Further, the time-length of the picture data stored in one address is selected to take into account those situations where picture data from the memory is subjected to some operation (e.g. some arithmetic operation is performed on the data).
Referring now to FIG. 1, there is shown a conventional video format signal processing circuit. In FIG. 1, an analog input video format signal (e.g. a signal which has been read-out from a video disk), is first sampled, and then quantized by an A/D (analog-to-digital) converter 1, thereby converting the analog input video signal into a digital signal. The digitized video format signal is then supplied to a S-P converter 2 so that the samples of the video format signal are combined into sets of M-samples. The sets of M-samples are then successively written (in the form of set of M-samples by set of M-samples) into respective addresses of a picture memory 3. Data of M-samples from the picture memory 3 is then successively read-out from the respective addresses of the memory in the order in which the data (of M-samples) was written into the respective addresses of the memory 3. The data of each set of M-samples read-out from the picture memory 3 is then supplied to a P-S converter 4 for successively supplying data of one sample (after data of one sample) into a D/A (digital-to-analog) converter 5. The data received by the D/A converter 5, from the P-S converter 4, is successively converted into an analog output video format signal having a phase which is different from that of the input video format signal. The video format processing system of FIG. 1 includes a controller 6 for controlling the timing of the processing system. The controller 6 is designed to generate conversion clocks a and b which are supplied to the S-P converter 2, and to the P-S converter 4, respectively. The controller 6 also generates a quantizing clock c which is supplied to the A/D converter 1.
In order for the system of FIG. 1 to perform high-speed data input/output, and in order to simplify the system, it is preferable to design the processing system such that the S-P converter 2 and the P-S converter 4 alternately operate. In other words, it is preferable to design a processing system in which either the S-P converter 2 or the P-S converter 4 operates at a given time, thereby allowing, for example, data to be subjected to S-P conversion while the P-S conversion is stopped, and vice-a-versa.
FIG. 2 shows the timing scheme for alternately or selectively controlling the S-P converter 2 and the P-S converter 4. More particularly, waveform (A) of FIG. 2 shows the timing for clock a, and waveform (B) shows the timing for clock b. As shown in FIG. 2, data is converted by the S-P converter 2 at the leading edge (L.E.) of the clock a. At that time (i.e. L.E. of clock a). data is written into the picture memory 3. On the other hand, data of 8-samples is read-out of the picture memory 3 and then is transferred to the P-S converter 4 at the leading edge of clock b. As shown in FIG. 2, clock b is shifted in phase from clock a by one-half of an 8-sample period. The data (of one set of 8-samples after data of one set of 8-samples) outputted from the P-S converter (i.e. L.E. of clock b). is successively supplied to the D/A converter 5 in response to a clock d which has the same frequency as that of the quantizing clock c (FIG. 1).
When the writing and reading operations are controlled according to the above timing scheme, the frequency of the clock c for quantizing a video format signal is selected to be, for example, 910 times the video horizontal frequency of the input video signal. Further, the period M of the S-P and the P-S conversion is selected to be 8 times that of the quantizing clock c so that the time length of data stored in one address of the memory is an integral multiple of the subcarrier period. However, when selecting the above values for the clock and period M. synchronization problems result.
More particularly, in order to perform writing and reading operations alternately into and out of a picture memory, it is necessary to make the frequency f.sub.c of the quantizing clock c divisible by the period M of the S-P and P-S conversion such that the quotient of (f.sub.c .div.M) is an integer. In the processing system described above, the frequency of the quantizing clock c was selected to be 910 times the horizontal line frequency of the video signal, and the period M was selected to be 8 samples. However, if 910 is divided by 8, the resulting quotient is 113.75 (which is not an integer). and therefore the writing and reading operations cannot be alternately and successively carried-out. Therefore, in order to make the resulting quotient equal to an integer, it is necessary to design a processing system which can consider only a section of data (i.e. data composed of samples which are integer times as many as 8). One such system would include 904 samples (904.div.8=113) for each horizontal period. In such a system, a portion of data (i.e. 904 samples) is written into the picture memory and the data of the remaining 6-samples (i.e. 910-904=6) is simply omitted.
In order for a processing system to handle only a section of data of each horizontal period, a timing scheme as shown in FIG. 3 has been proposed, wherein waveform (A) of FIG. 3 represents an input video format signal, and waveform (B) represents clock a of FIG. 1. More particularly, clock a is inhibited or stopped when the writing operation of 904 samples has occurred (point of time t.sub.1). and the starting of the S-P conversion period is reset by a write-in starting pulse generated from a horizontal synchronizing signal or a burst signal of the input video format signal (point of time t.sub.2). Thus, the video data can be written into predetermined addresses of the memory under the condition that each data portion corresponding to 8 quantizing or sampling clocks is to be stored into one address of the memory. FIG. 4 shows an enlarged diagram of clock a in a period including the points of time t.sub.1 and t.sub.2 of FIG. 3. As shown in FIGS. 4, 6 samples of the video occur within the interval between times t.sub.1 and t.sub.2, and are not written into the memory.
As shown in FIG. 5, waveforms (A) and (B) represent the video format signals e, and f, which are written-into, and read-out of the picture memory 3, respectively, and which have a phase difference therebetween corresponding to a difference between the writing and the reading addresses of the picture memory 3, and the so-called synchronization conversions are performed according to the phase difference. FIGS. 6-8 show the periods of S-P and P-S conversion for the synchronization conversion. In FIGS. 7 and 8, a reset position (point of time t.sub.3) of the write-in starting point, and a reset position (point of time t.sub.4) of the read-out, starting point are shown which correspond to FIG. 5. FIG. 6 shows the waveforms (A) and (B) of the clocks a and b, respectively. FIG. 7 is an enlarged diagram, wherein waveforms (A) and (B) show the clocks a and b, respectively, in a period including the point of time t.sub.3, and FIG. 8, is enlarged diagram showing the waveforms (A) and (B) of the clocks a and b, respectively, in a period of time including the point of time t.sub.4. In the interval between the points of time t.sub.3 and t.sub.4, the clocks a and b are made to be anti-phase or opposite to each other, so that the data-writing and the data-reading operations into and out of the picture memory, respectively, can be alternately or selectively performed. Referring to FIG. 8, in the other sections or intervals (e.g. after time t.sub.4), however, the anti-phase state is not maintained after the reset operation, so that the data writing-into and data reading-out operations of the picture memory 3 cannot be alternately performed.
In order to maintain the anti-phase relationship between clocks a and b outside of the interval between t.sub.3 and t.sub.4, it has been suggested that the clocks a and b be phase-modulated so that clocks a and b do not overlap each other outside of the interval between t.sub.3 and t.sub.4. Such a phase-modulating method has been used in broadcasting equipment; however, the phase-modulating method introduces problems into the processing system. More particularly, the phase-modulating method requires a complicated circuit arrangement for the memory controller, and further, the method requires high-speed components for the picture memory, the S-P converter, the P-S converter, the memory controller, etc. These high-speed components provide the required time for performing various timings, and necessarily increase the power consumption of the system.
Thus, there is a continuing need in the video format processing art for a system which can operate as indicated above, and which is relatively simple in design, and which does not consume a prohibited amount of power.